The present invention relates generally to digital to analog converters and more particularly to digital to analog converters having a resistor ladder and switching network of the R-2R ratio type.
An inherent problem with conventional digital to analog (D/A) converters employing R-2R ladder networks for offset binary operation with zero mean signals is that the ideal or small signal output level about mid scale is at the major switching point. Since this major switching point generates the maximum switching noise and error, the signal-to-noise ratio is reduced at precisely the point where the signal is at its minimum. To illustrate this problem, and to provide a standard for comparison with the present invention, a conventional D/A converter 100 having a four bit signal resistor ladder is shown in FIG. 1. Although only four bit signals are employed in this example, any length of ladder could be used with no loss of generality.
In FIG. 1, converter 100 includes switching network means 110 responsive to a binary code of digital signals representative of electrical conditions or characteristics, such as voltage or current. In response to this binary code, switching means 110 completes electrical paths to resistor stages 120, 140, 160, and 180 such that bit signals A, B, C, and D, corresponding to each of these resistor stages respectivey, may pass to line 105, and, through series resistors 101, 102, and 103, to a common output. The resistor ladder is terminated with series terminating resistor 106, which is returned to some fixed signal level, V.sub.bias. The sum of these electrical signals at the common output is an analog representation of the digital signals.
The coding action of the resistor ladder and switching network for converter 100, in terms of logical "1s" and "0s" input to converter 100 by switching means 110, is shown below in Table 1 on a step by step basis from lowest to highest output.
Any standard text will explain the operation of this resistor ladder converter in detail. The important points are that the ladder is built with resistors in the ratio of R-2R and that the bit signals driving the ladder all change value as the ladder output goes through mid scale. A zero mean signal, such as that commonly generated by voice or video signals, will be centered at the mid scale, and as the variance of the signal becomes smaller, a progressively larger percentage of the total noise generated will be that contributed by the mid scale or major switching point errors.
In the limit, where the signal is so small that it transverses only the mid scale switching point, the signal-to-noise ratio will be the root means square value of the signal, divided by the root means sum of the inherent quantization error and the ladder and switching error. Since all resistor ladder stages change state at this point, any errors due to either ladder resistor or ladder switches will be maximized at this switching point. At this error maximum the converter may lose monotonicity. A significant portion of the noise added to a signal generated by such a digital to analog converter will result from the sum of all the errors generated by switching. Anything which be done to reduce this source of error will directly improve the signal-to-noise ratio.
TABLE 1 ______________________________________ Bit Signal: Output Number of A B C D Level: Switches: ______________________________________ 0 0 0 0 1/16 0 0 0 0 1 1/8 1 0 0 1 0 3/16 2 0 0 1 1 1/4 1 0 1 0 0 5/16 3 0 1 0 1 3/8 1 0 1 1 0 7/16 2 0 1 1 1 1/2 1 Mid Scale: 1 0 0 0 9/16 4 1 0 0 1 5/8 1 1 0 1 0 11/16 2 1 0 1 1 3/4 1 1 1 0 0 13/16 3 1 1 0 1 7/8 1 1 1 1 0 15/16 2 1 1 1 1 1 1 ______________________________________